It is generally recognized that integrated circuits are susceptible to damage from electrostatic discharge (ESD). Such damage generally occurs when current and/or voltage ratings of devices in an integrated circuit are exceeded.
Progress in VLSI technology today has resulted in smaller and smaller integrated circuit geometries in integrated circuits. With scaled-down device dimensions, shallow junction depths, thinner gate oxides, lightly doped drain (LDD) structures, and the use of salicide process technology, integrated circuits generally become more susceptible to ESD damage. This becomes more severe when the integrated circuit consists of multiple independently-powered circuit sections (e.g., sections of the integrated circuit having isolated power rails). For example, both externally-applied DC and alternating current (AC) power sources are configured to provide a nominal power supply, or standard voltage, to an integrated circuit (IC) for its operation. On occasion, these power sources may pass to the IC transient or sustained voltages that are significantly above nominal level. In addition, human handlers and/or electronic equipment may carry or generate a significant static electrical charge, sometimes on the order of a thousand to two thousand volts or more. For example, when a human handler inadvertently touches the leads of an IC and passes such a high static charge to an input buffer on the IC, significant (and sometimes fatal) damage can be done to the IC if the IC is without some kind of protection against such ESD.
The Human Body Model (HBM) is a commonly used model for characterizing the susceptibility of an electronic device to damage from ESD. The model is a simulation of the discharge which might occur when a human touches an electronic device. The Machine Model (MM) is an alternative ESD model representing a discharge similar to the HBM event from a charged conductive object, such as a metallic tool or fixture. The Charged Device Model, in contrast, represents a transfer of charge from an ESD protection device. A CDM event can be more destructive than an HBM event for some devices. Although the duration of the discharge is very short (e.g., often less than one nanosecond) the peak current can reach several tens of amperes. Generally, the ESD robustness of integrated circuit devices should exceed 2 kV for HBM ESD events, 200V for MM events, and/or 500V for CDM events. It is often desirable to design integrated circuits that can satisfy these requirements with some margin of safety.
In advanced VLSI integrated circuit devices, power lines may be separated to avoid noise coupling and to reduce ground bouncing for high-performance circuit operation. In addition, an integrated circuit device may have multiple power supplies for different types of input and/or output (I/O) signals. These supplies could be at different voltage levels. For example, a CMOS I/O may operate at 3.3 v, a double data rate (DDR) RAM I/O may operate at 2.5 v, and a low voltage differential signaling (LVDS) I/O may operate at 1.8 v. Conventionally, a separate ESD protection device is provided for each power rail.
Referring now to FIG. 1, an integrated circuit 100 having independent power supply rails 111 and 121 is shown. Power supply rail 111 may operate at 3.3 v and have a first ESD clamp 112. Power supply rail 121 may operate at 1.8 v and have a second ESD clamp 122. ESD clamps 112 and 122 may comprise one or more of a silicon-controlled rectifier (SCR), an RC-triggered shunt, a stacked diode, a breakdown MOSFET, or any other ESD clamp device known in the art.
Referring now to FIG. 2A, a conventional RC-triggered shunt device 200 is shown. During an ESD event, the RC circuitry generally pulls the intermediate node 203 low and in turn biases the gate of transistor 202. Transistor 202 is typically an NMOS device having total device width (W) of more than 1000 μm. When the gate of transistor 202 is biased at a voltage above a certain threshold, the transistor will turn on and create a short between power lines 210 and 211 to shunt the ESD current. Many factors must be considered when designing an RC-triggered shunt circuit. The combination of resistor 201 and capacitor 204 generally determines the period during which the RC shunt will be active during an ESD event. However, resistor 201 and capacitor 204 must also be selected such that, during normal operation (e.g., in the absence of an ESD event), the voltage at node 203 is high enough to keep inverter 205 tied low, so that transistor 202 remains turned off. Typical RC shunt delays are in the range of 1 to 5 micro-seconds (μs). The delay has much different magnitude from the rate of power ramping, which usually falls in the millisecond (ms) range. Accordingly, a circuit designer would not configure the RC shunt to have a delay near the millisecond range, to avoid a false triggering of the RC shunt device during a ramp of the power supply. Furthermore, in inverter 205 a PFET transistor 206 is generally much larger than the NFET transistor 207, in order to facilitate fast activation of the shunt device 200 when an ESD event occurs.
Another conventional ESD shunt device is the stacked diode chain. Referring now to FIG. 2B, diode chain 220 is shown. Diode chain 220 includes a plurality of diodes (e.g., diodes 221, 222, and 223) connected in series. The diodes in a diode chain are implemented with diode-connected transistors. Referring now to FIG. 2C, a diode chain 220′ is shown, comprising diode-connected transistors 221′, 222′, and 223′. Diode-connected transistors 221′, 222′, and 223′ are PNP-based transistors. More specifically, transistors 221′, 222′, and 223′ may be connected as P+/N-well diodes. Because diodes are susceptible to noise, the diode chains 220 and 220′ might be triggered after a temperature or other operational variation. Therefore, diode chain-based ESD clamp devices are usually designed with a safe margin between the turn-on (e.g., ESD activation) voltage and the maximum operating voltage of the circuit to be protected. Diode chain 220′ is also subject to current leakage during normal operation. For example, when diode-connected transistor 221′ is turned on, there is a collector current Ileak that flows to substrate 225.
Therefore, proper care must be taken to limit the total current leakage in order to prevent circuit malfunctions and to reduce the total power consumed by the integrated circuit device.
With the conventional approach (e.g., where a separate ESD clamp is provided for each power rail, as shown in FIG. 1), the number of ESD clamp devices increases somewhat dramatically as the number of isolated and/or different power supply rails increases. In addition, ESD protective structures may consume a relatively substantial portion of a semiconductor die that is manufactured using modern manufacturing processes (e.g., 0.13 μm, 90 nm, 65 nm, etc.). Thus, larger structures such as ESD clamps may be relatively more expensive to produce in a smaller manufacturing process than in an older manufacturing process (e.g., 0.18 μm, 0.25 μm, etc.).
Therefore, it would be desirable to provide an ESD protective device that can be shared by independent power supply rails, while also limiting the amount of leakage current, thereby reducing the total number of ESD protective devices in and/or on a mixed supply voltage integrated circuit device.